I am seriously contemplating reverting back to RT 7.1, considering I don't have much time to do extra R&D. If I have missed something or done something improper. The above process yields 80% with the NPL Vi's and only 5% in the TCL.
Reassociated the RT host Vi's with the newly compiled FPGA Vi's and target. Recompiled both these Vi's with the right target.
#NI OPC SERVER HIGH CPU AND MEMORY USAGE CODE#
Updated the FPGA code with the new IO Alias's Mapping in the VI. Reassigned/Remapped all the IO points for the FPGA VI's within the project Added the existing VI's, which resulted in missing IO mapping So I erased the FPGA targets from the Host computer and recreated them in the RT target. However, I got an error saying "Resources/Targets not found" because it did not create them under my RT Target.(Go figure) opened up my Polling code and refreshed/reassigned the resource and VI. First opened up the FPGA Migration utility to convert them to 8.0. Without the option unchecked, I can't get a CPU Usage % display (NaN).īelow I am mentioning the steps which I have taken to ensure that I have migrated correctly. If the NPL is used, the CPU is AFTER I disable/uncheck the Memory usage in the RTSM. If I run my TCL loop by itself, I see 5% usage in LV8. (I simply don't understand why the same code in LV7.1.1 does not yield the same result.) It is next to impossible to locate this issue. The RTSM shows a usage of 10-12% So FGV's can me ruled out?Ģ)Based on the above attached example, using real live data from the 7831R & 7833R, my CPU usage is just for the polling. I tried two examples to isolate the problem.ġ)A simple VI which has a TC VI writing values using an FGV and a NPL picking them up. Unfortunately, the results are very inclusive. I finally found some time which allowed me to test the suggestions of the AE's and forum replies.
Its been a while since I had some updates on this issue. Hope this helps, please let me know if you have more questions.
#NI OPC SERVER HIGH CPU AND MEMORY USAGE HOW TO#
Observe if it is going to 100% or notĪlso you may want to refer to the following links that recommend how to prevent the cpu usage going to 100%. The clock rate will be as mentioned in step 1ģ) Also in the normal priority loop increase the wait time a little and observe the cpu usageĤ) Use the shared variable with the RT communication wizard and do a simple read and write. You may try doing the following:ġ) In the timed loop set the source name to be 1KHz and the period to be one, this way you are not taking too much cpu usage and wasting the 999 cyclesĢ) In fact go ahead and just use the regular while loop as time critical as opposed to using a timed loop. Since using shared variables with a RT FIFO also gives a cpu usage of 100% this makes me think it is most likely it is specific your code. This should allow you to revert back to Real-Time 7.1.įor the first question, it is very interesting that it works with 7.1.1 and not in 8.0. The answer to your second question is that to move from 8.0 Real-Time to 7.1 your will need to uninstall the Network Variable Engine and the Variable Client Support from your RT device. Does anyone know the dependencies required to bring it back to 7.1 through the MAX "add/remove software"? This doesn't make sense to me, in theory what works in LV 7.1 should work in 8.0.Īlso, I cannot switch to LV7.1 once 8.0 is installed. if i disable the reading of the FGV's, my idle usage with polling is 20%. I also tried using the so called "Shared variables w/FIFO's enabled" and the result is still the same. ( I disabled every other loops/ tasks inorder to come down to this conclusion). However, the FGV?s in Labview 8 are hogging up the resources and that seems to be the bottle neck.
The processing would be comparing values, storing to disk etc. I have attached a screen shot of my 7.1 Vi's which have been migrated to 8.0. However in labview 8 it?s a constant 100%. In Labview 7.1 my CPU Usage never exceed 40%. After polling I use a FGV to transfer it out into a normal priority thread and process it.
I usually poll the FPGA cards in a time critical VI, (I have 2 FPGA cards). I use "RT Simple CPU Usage.VI" to check the CPU resources. I have a very STRANGE issue here, I migrated my working Labview 7.1.1 RT code to Labview 8.0 and noticed the performance degradation beyond acceptance level.:smileymad: